The following Patent Document 1 discloses a known semiconductor device which comprises a metallic support plate, first and second transistors piled up in turn on the support plate, third and fourth transistors piled up in turn on the support plate, and a control circuit (control IC) mounted on the support plate and between the first and second transistors and between the third and fourth transistors to cause the first, second, third and fourth transistors to form an H-type bridge circuit. In Patent Document 1, first and second transistors are stacked, and third and fourth transistors are stacked to reduce occupation space of the support plate and increase the integration degree of the device.
Also, in the semiconductor device of Patent Document 1, each lower electrode formed on the bottom surface of second and fourth transistors is secured by solder on each upper electrode formed on the top surface of first and third transistors, and upper electrodes of first and third transistors are electrically connected via wires to an upper electrode of the control circuit and a plurality of outer leads disposed around the support plate. The direct electric connections by solder between first and second transistors and between third and fourth transistors serve to advantageously shorten flow paths of electric current while preventing noise and power loss which may occur with an elongated flow path and also simplifying wiring connections.
[Patent Document 1] WO 2005/018001